note: for detailed information on purchasing options, contact your local allegro field applications engineer or sales representative. allegro microsystems, inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no respon- sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. recommended substitutions: low voltage full bridge brushless dc motor driver with hall commutation and soft switching, and reverse battery, short circuit, and thermal shutdown protection A1442 for existing customer transition, and for new customers or new appli- cations, contact allegro sales. date of status change: december 10, 2012 deadline for receipt of last time buy orders: may 31, 2013 this part is in production but has been determined to be last time buy. this classification indicates that the product is obsolete and notice has been given. sale of this device is currently restricted to existing customer applications. the device should not be purchased for new design applications because of obsolescence in the near future. samples are no longer available. last time buy
description the A1442 is a full-bridge motor driver designed to drive low- voltage, brushless dc motors. commutation of the motor is achieved by use of a single hall element to detect the rotational position of an alternating-pole ring magnet. a high-density cmos semiconductor process allows the integration of all the necessary electronics. this includes the hall element, the motor control circuitry, and the full output bridge. low-voltage design techniques have been employed to achieve full device functionality down to low v dd values. this fully integrated single chip solution provides enhanced reliability (including reverse battery protection and output short circuit protection) and eliminates the need for any external support components. the A1442 employs a soft-switching algorithm to reduce audible switching noise and emi interference. a micropower sleep mode can be enabled by an external signal, to reduce current consumption for battery management in portable electronic devices. this feature allows the removal of a fet transistor for switching the device on and off. the A1442 is optimized for vibration motor applications in cellular phones, pagers, electronic toothbrushes, hand-held video game controllers, and low power fan motors. the small package outline and low profile make this device ideally suited for use in applications where printed circuit board area and component headroom are at a premium. it is available in a lead (pb) free, 6 pin mlp/dfn microleadframe package, with an exposed pad for enhanced thermal dissipation. A1442-dsw, rev. 2 features and benefits ? low voltage operation ? reverse voltage protection on vdd and s l e e p pins ? output short circuit and thermal shutdown protections ? soft switching algorithm to reduce audible switching noise and emi interference ? unidirectional working mode provides motor rotation in one direction ? hall chopper stabilization technique for precise signal response over operating range ? sleep mode pin allowing external logic signal enable/ disable to reduce average power consumption ? antistall feature guarantees continuous rotation ? low current consumption sleep mode ? single-chip solution for high reliability ? miniature mlp/dfn package low voltage full bridge brushless dc motor driver with hall commutation and soft switching, and reverse battery, short circuit, and thermal shutdown protection package: 6 pin mlp/dfn (suffix ew) functional block diagram approximate scale A1442 1.5 mm 2 mm, 0.40 mm maximum overall height am hall element p reverse battery power and sleep mode control active braking control stall detection drive logic and soft switching control gnd vdd vout1 output full bridge q1 q3 q2 q4 sleep vout2 thermal shutdown protection m 0.1 f
low voltage full bridge brushless dc motor driver with hall commutation and soft switching, and reverse battery, short circuit, and thermal shutdown protection A1442 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings characteristic symbol notes rating units forward supply voltage v dd 5.0 v reverse supply voltage v rdd ?5.0 v output voltage v out v dd > 0 v 0 to v dd + 0.3 v reverse output voltage v rout v dd > 0 v ?0.3 v s l e e p input voltage v in 0 to v dd + 0.3 v peak output current i outpk < 1 ms 400 ma operating ambient temperature t a range e ?40 to 85 oc junction temperature t j (max) 165 oc storagetemperature t stg ?65 to 165 oc selection guide part number package 1 packing A1442eewlt-p 2 mlp/dfn 1.5 mm 2 mm, 0.4 mm maximum overall height 3000 pieces / 7 in. reel 1 contact allegro ? for additional packing options. 2 allegro products sold in dfn package types are not intended for automotive applications. pin-out diagram terminal list table pin name function 1 vdd supply voltage 2 s l e e p toggle sleep/enabled modes 3 nc no connection 4 gnd ground 5 vout1 first output 6 vout2 second output vdd sleep nc vout2 vout1 gnd pad 6 5 4 1 2 3
low voltage full bridge brushless dc motor driver with hall commutation and soft switching, and reverse battery, short circuit, and thermal shutdown protection A1442 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com operating characteristics valid over the full v dd and t a range unless otherwise noted characteristic symbol test conditions min. typ. max. units supply voltage 1 v dd operating, t j < t j (max); c byp = 0.1 f 2.0 ? 4.2 v supply current i dd(on) v in >v inhi, , t a = 25c , no load ?4 6ma v in < v inlo , t a = 25c ?? 10 ? a total output on resistance 2,3 r ds(on) v dd = 2 v, i out = 70 ma, t a = 25c ? 3.9 ? v dd = 3 v, i out = 70 ma, t a = 25c ? 2.6 ? v dd = 4 v, i out = 70 ma, t a = 25c ? 2.2 ? reverse battery current i rdd v rdd = ?4.2 v ? ? ?10 ma sleep input threshold v inhi 0.7v dd ?v v inlo ? ? 0.2v dd v sleep input current i in v in = 3.0 v ? 1.0 5 ? a reverse sleep current i rin v rin = ?4.2 v ? ? ?10 ma restart delay 4 t rs ? 120 ? ms hall chopping settling time t s(chop) ?80 ? ? s magnetic switchpoints 2 b op ?35 75 g b rp ?75 -35 ? g b hys ?70 ? g output polarity v out1 b < b rp ? low ? v b > b op ? high ? v v out2 b < b rp ? high ? v b > b op ? low ? v 1 a bypass capacitor of 0.1 f is required between vdd and gnd for proper device operation through the full specified voltage range. 2 extended v dd range affects r ds(on) and b x . 3 total on resistance equals either r ds(on) q1 + r ds(on) q4 or r ds(on) q2 + r ds(on) q3. 4 the restart delay is the time the outputs are on or off when the device is attempting a restart.
low voltage full bridge brushless dc motor driver with hall commutation and soft switching, and reverse battery, short circuit, and thermal shutdown protection A1442 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description soft switching the A1442 device includes a soft-switch- ing algorithm that controls the output switching slew rate for both output pins. as a result the A1442 device is ideal for use in applications requiring low audible switching noise and low emi interference. sleep mode the s l e e p pin accepts an external signal that enables sleep mode. in sleep mode, the current consumption is reduced to an extremely low level, conserving battery power in portable electronics. antistall algorithm if a stall condition occurs, the device will execute an antistall algorithm. device start-up the start-up behavior of the device output is determined by the applied magnetic field, as specified in the operating characteristics table. 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v dd (v) r ds(on) ( ) total output on-resistance versus supply voltage i load = 150 ma characteristic performance
low voltage full bridge brushless dc motor driver with hall commutation and soft switching, and reverse battery, short circuit, and thermal shutdown protection A1442 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com application information two typical application circuits are shown in figures 4 and 5. the first application circuit shows the device s l e e p pin controlled by the user. figure 5 illustrates an application circuit where the device vdd and s l e e p pin are connected together. note that: ?? no external diode is required for reverse battery protection because the protection is fully integrated into the ic. ?? thermal shutdown is integrated also. a bypass capacitor of 0.1 f is required between vdd and gnd for proper device operation through the full specified supply volt- age range. m + v batt c byp A1442 nc vdd i/o system logic control gnd vout1 sleep vout2 figure 4. application circuit showing user-controlled sleep/enable mode, while the A1442 remains powered at all times m + v batt c byp A1442 nc vdd i/o system logic control gnd vout1 sleep vout2 figure 4. application circuit showing simultaneous user control of power supply and sleep mode.
low voltage full bridge brushless dc motor driver with hall commutation and soft switching, and reverse battery, short circuit, and thermal shutdown protection A1442 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com power derating m + v batt c byp 0.1 f A1442 nc vdd i dd i/o system logic control gnd vout1 i l sleep vout2 figure 4. typical application showing current paths the device must be operated below the maximum junction tem- perature of the device, t j (max). under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the appli- cation. this section presents a procedure for correlating factors affecting operating t j . (thermal data is also available on the allegro microsystems web site.) the package thermal resistance, r ja , is a figure of merit summarizing the ability of the appli- cation and the device to dissipate heat from the junction (die), through all paths to the ambient air. its primary component is the effective thermal conductivity, k, of the printed circuit board, including adjacent devices and traces. radiation from the die through the device case, r jc , is relatively small component of r ja . ambient air temperature, ta , and air motion are significant external factors, damped by overmolding. the effect of varying power levels (power dissipation, p d ) can be estimated. the fol- lowing formulas represent the fundamental relationships used to estimate t j at given levels of p d . given: p d = v in i in , (1) t = p d r ja , and (2) t j = t a + t (3) for a load of 30 , given common conditions such as: t a = 25c, v dd = 3 v, i dd = 83 ma, v l = 2.43 v, i l = 81 ma and r ja = 250 c/w, then: p d = v dd i dd ? v l i l = 3 v 83 ma ? 2.43 v 81 ma = 52.17 mw , t = p d r ja = 52.17 mw 250 c/w = 13c , and t j = t a + t = 25c + 13c = 38c a worst-case estimate, p d (max), represents the maximum allow- able power level, without exceeding t j (max), at a selected r ja and t a .
low voltage full bridge brushless dc motor driver with hall commutation and soft switching, and reverse battery, short circuit, and thermal shutdown protection A1442 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package ew, 6 pin mlp/dfn seating plane 0.38 0.02 0.70 0.10 1.25 0.05 0.25 0.05 1.10 0.10 1.10 0.30 0.70 1.575 0.50 0.325 2.00 0.15 1.50 0.15 c 0.08 7x 0.325 +0.055 ?0.045 0.50 bsc a 1 1 6 6 1 6 a terminal #1 mark area b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only, not for tooling use (refernce dwg-2856; similar to jedec type 1, mo-229x2bcd) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c reference land pattern layout (reference ipc7351 son50p200x200x100-9m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) active area depth 0.15 mm ref e e c b hall element (not to scale) f f f f 0.89 0.99 pcb layout reference view c branding scale and appearance at supplier discretion g g d d coplanarity includes exposed thermal pad and terminals standard branding reference view n = last two digits of device part number y = last digit of year of manufacture w = week of manufacture nn yww 1
low voltage full bridge brushless dc motor driver with hall commutation and soft switching, and reverse battery, short circuit, and thermal shutdown protection A1442 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com for the latest version of this document, visit our website: www.allegromicro.com copyright ?2006-2011, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. revision history revision revision date description of revision rev. 2 october 26, 2011 update selection guide
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